### 2-Input NAND Gate using 2:1 Multiplexer - Basic Gates design using MUX

Multiplexer can be used to design any combinational logic circuit. Here you would see how to implement a 2-input NAND gate using a 2:1 multiplexer - Basic Gates design using MUX

__2-Input NAND Gate using 2:1 Multiplexer - Basic Gates design using MUX__

### Step 1: To write the Boolean function of the gate to be designed

Here a 2-input NAND gate is to be designed using a 2:1 Multiplexer.

Truth table of 2-input NAND gate is:

A |
B |
Y |

0 |
0 |
1 |

0 |
1 |
1 |

1 |
0 |
1 |

1 |
1 |
0 |

Therefore, Boolean Function of NAND Gate would be

Y(A, B) = Σm(0, 1, 2)

### Step 2: To find number of select lines and input lines of the Multiplexer

For n variable Boolean function, the number of select lines of multiplexer (MUX) would be (n-1).

As we know that for a 2:1 MUX number of select lines would be 1. In this case there are two variables A & B.

i.e., n = 2

Therefore, Number of select lines would be n-1 = 1.

The variable B (LSB) would be used as select lines.

And variable A, which is the MSB, would be taken as the input variable.

### Step 3: Formation of Implementation Table

Write the MSB, i.e. A, at the left side of the table column wise and the other variable i.e., B at the top of the table row wise sequentially as shown below:

Write numbers from 0 to 3 in the cells of the implementation table.

Encircle the numbers or minterms given in the question.

If both the numbers in a column are encircled, then put ‘1’ against the corresponding input line ‘I’.

If both the numbers in a column are not encircled, then put ‘0’ against the corresponding input line ‘I’.

If only one number is encircled in a particular column, then
write its corresponding MSB i.e., A or A^{/} against its input line
‘I’.

### Step 4: To draw the circuit for implementing 2-input NAND Gate using 2:1 MUX

As seen from the implementation table, to design a 2-input NAND Gate, connect the input I_{0} of the 2:1 multiplexer to 1 and the input I_{1} to ‘A^{/}’ .

In this way a 2 input NAND Gate can be implemented using a 2:1 multiplexer.

Hope this post on "**2-Input NAND Gate using 2:1 Multiplexer - Basic Gates design using MUX**" would help in clearing many doubts in Multiplexer.

__Related links:__

- Implementation of Boolean Function using Multiplexer
- 2-Input AND Gate using 2:1 Multiplexer - Basic Gates design using MUX
- 2-Input OR Gate using 2:1 Multiplexer - Basic Gates design using MUX
- 2-Input XNOR Gate using 2:1 Multiplexer - Basic Gates design using MUX
- 2-Input NOR Gate using 2:1 Multiplexer - Basic Gates design using MUX
- 2-Input XOR Gate using 2:1 Multiplexer - Basic Gates design using MUX

__Some Other Links:__

__Some Other Links:__

- Flip-flop Conversion – SR
flip-flop to JK flip-flop
- Flip-flop Conversion – SR
flip-flop to D flip-flop
- Flip-flop Conversion – JK flip-flop to D flip-flop
- Flip-flop Conversion – D
flip-flop to SR flip-flop
- Flip-flop Conversion – JK
flip-flop to SR flip-flop
- Flip-flop Conversion – JK
flip-flop to T flip-flop
- Flip-flop Conversion – T
flip-flop to D flip-flop
- Flip-flop Conversion – T flip-flop to SR flip-flop
- Flip flop Conversion – D flip-flop to T flip-flop
- Flip flop Conversion – SR
flip-flop to T flip-flop
- Flip flop Conversion – T flip-flop to JK flip-flop
- Flip flop Conversion – D flip-flop to JK flip-flop

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